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<dc:identifier>ISBN:81-297-0537-0</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=21241</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8129705370.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Palnitkar, Samir.<br /> New Delhi Pearson Education Publisher 81-297-0537-0 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=21241">Place hold on <em>Design Verification</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=21241</guid> </item> <item> <title> Verilog HDL A Guide to digital design and synthesis . </title> <dc:identifier>ISBN:81-297-0092</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=21287</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Palnitkar , Samir.<br /> New Delhi Pearson Education Publisher 81-297-0092 </p> ]]> <![CDATA[ <p> <a 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<em>Verilog HDL</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=21290</guid> </item> <item> <title> Verilog HDL A Guide to digital design and synthesis </title> <dc:identifier>ISBN:978-81-7758-918-4</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=21291</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8177589180.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Palnitkar , Samir.<br /> India Pearson Education Publisher 2019 978-81-7758-918-4 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=21291">Place hold on <em>Verilog HDL</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=21291</guid> </item> <item> <title> Verilog HDL A guide to Digital Design and Synthesis </title> <dc:identifier>ISBN:81-297-0092-1</dc:identifier> <!-- prettier-ignore-start --> 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