| 000 | 00825nam a2200241Ia 4500 | ||
|---|---|---|---|
| 001 | PAD-DES-HDL-9812-53-131-9 | ||
| 005 | 20260729074612.0 | ||
| 008 | 260729s9999 xx 000 0 und d | ||
| 020 | _a9812-53-131-9 | ||
| 040 | _cPK-LaCU | ||
| 041 | _aEnglish | ||
| 082 |
_a621.392 PAD _bPAD |
||
| 100 | _aPadmanabhan, T.R. | ||
| 245 | 0 | _aDesign through Verilog HDL | |
| 260 |
_aNew York _bJohn Wiley & Sons Publisher |
||
| 300 | _bSoft Binding | ||
| 365 |
_b1000 _cRs. |
||
| 521 | _aFaculty, students and Staff | ||
| 650 |
_aElectrical Engineering _xVerilog HDL |
||
| 856 |
_uhttps://libgen.is/book/index.php?md5=A1A97691407A885D673BF8670892AF3E _yPlease click to web link toaccess the online resource |
||
| 942 |
_2DDC _cBK _hPAD |
||
| 999 |
_c21154 _d21154 |
||